The present invention relates to a semiconductor memory using dynamic memory cells, and particularly to a technology effective for application to the speeding up of a semiconductor memory having a redundant circuit and a reduction in power consumption.
As a storage elemental device used in various electronic apparatuses, there is known a dynamic random access memory (hereinafter called a “DRAM”), which needs regular refresh to hold memory information therein although it has an advantage in that it is high in the degree of integration and low in bit cost. Thus, the dynamic random access memory is normally used together with a memory controller having a refresh command issuing function. This is unsuitable for a small-sized system like a cellular phone. A static random access memory (hereinafter called simply an “SRAM”) is principally used as a storage elemental device for the small-sized system at present. With high functionality of portable equipment, however, there has been an increasingly demand for a larger-capacity storage elemental device. Therefore, the SRAM has not been brought into line with costs of production.
A method of eliminating the need for refresh of a DRAM from outside has been disclosed in Unexamined Patent Publication No. Sho 61(1986)-71491. This is a method of dividing one cycle into two time zones or slots and performing refresh in the first half and performing a read or write operation in the last half. If done in this way, then the refresh operation can be concealed from outside, and a DRAM low in bit cost can be used in a manner similar to the SRAM (as a pseudo SRAM).